1. Field of the Invention
The present invention relates to a pattern data preparing method for a mask used in manufacturing a semiconductor device, a mask pattern data preparing method, a mask manufacturing method, a semiconductor device manufacturing method, and a program recording medium.
2. Description of the Related Art
Progress in semiconductor manufacturing technology in recent years has been remarkable, and semiconductor devices of a size of 0.13 μm, which is the minimum process dimension, have been produced in large quantities. Such miniaturization is realized by the rapid progress in fine pattern forming technology such as a mask process technology, photo lithography technology, and an etching technology.
In the days when pattern sizes were sufficiently large, a pattern simultaneously the same as a design pattern could be formed on the wafer in such a manner that the desired plane shape of an LSI pattern was drawn as is as a design pattern on a wafer; a mask pattern faithful to the design pattern was prepared; the mask pattern was transferred on the wafer by a projective optical system; and the underlying layer is etched.
However, as miniaturization of patterns has progressed, it has been difficult to faithfully form patterns in respective processes, and as a result, the problem that final finished dimensions are not made to be as the same as a design pattern has been brought about.
In order to solve such a problem, means (hereinafter, mask data process) for preparing a mask pattern different from a design pattern such that the final finished dimensions thereof are made equal to the design pattern dimensions in consideration of a conversion difference in each process have been extremely important.
As mask data process, there is a graphics computing process or a MDP (mask date process) process which changes a mask pattern by using a design rule checker (D. R. C.), or the like, and in recent years, there are optical proximity correction (OPC) process for correcting an optical proximity effect (OPE), and the like. By carrying out these processes, a mask pattern is appropriately corrected such that the final finished dimensions thereof are made to be desired dimensions.
However, in a device, such as a logic device, for which a longer TAT (Turn Around Time) is required, an increase in a process time required for mask data process directly causes an increase in TAT. One the other hand, in order to prepare a device so as to reduce the burden due to mask data process, it is necessary to relax design rules (hereinafter, D. R.). There is a risk that the relaxation in D. R. brings about a reduction in competitiveness due to an increase in a chip size.
Here, D. R. includes all rules for putting restrictions on a design layout. D. R. includes, not only layout restrictions according to a line width of a pattern, a distance of a space between patterns, and the like which have been conventionally used, but also layout restrictions according to a shape of a pattern (corners and line ends) and the like. Moreover, with respect to specifying layout restrictions, there are cases in which a layout is restricted, not only in units of dimensions (distances), areas, and the like, but also in accordance with an amount of transformation in dimensions (a resized amount) with respect to a pattern. In this way, D. R. is the general term for all rules for restricting a layout.
In order to decide D. R. under which both of an improvement in a TAT and a reduction in a chip size can be achieved, and a burden due to mask data process, there is proposed a method in which a design layout predicted to be used in the next generation is acquired by carrying out compaction onto the design property in the previous generation on the basis of D. R. used for the next generation, mask data process and lithography simulation are carried out by using the design layout, and an evaluated result thereof is fed back to D. R. (Jpn. Pat. Appln. KOKAI Publication No. 2002-26126).
In this method, because D. R. can be decided on the basis of, not only a basic pattern of a device such as that of a prior art, but also a pattern which is similar to a layout for use in an actual device, it is possible to present D. R. in which problems which may be actually brought about have been avoided in advance.
However, even if a design layout is prepared under the D. R. presented by this method, a chip size is not always made minimum. The reason for this is that, if the D. R. corresponding to a pattern having a problem are relaxed, patterns without any problem other than the pattern are relaxed, which increases a chip area in vain.
Here, a method in which D. R. are set such that only problems can be extracted by increasing the types of D. R. can be considered, but, it is impossible to allocate separate D. R. to all types of patterns. Further, due to D. R. being made complicated, difficulties such as an increase of burden on a designer preparing a design layout, a complexity in a verification by D. R. C., and the like are brought about.
If it is difficult to express all types of patterns by D. R., there is a risk that patterns which cannot be formed on a wafer in accordance with predetermined specifications provided (hereinafter, called risk patterns) are generated in at least some of the types of patterns. On the other hand, because D. R. is intimately interrelated with a chip area, a chip area is increased if numeric values of D. R. are roughly set. Accordingly, it is important to appropriately set D. R. by finding out a correlation among the number and types of risk patterns, a chip area, and D. R.
Moreover, the number of risk patterns and a chip area change in accordance with, not only the setting of D. R., but also process parameters (including parameters for mask data process).
For example, even under predetermined D. R., the number of risk patterns and a chip area are made to fluctuate when an exposure wavelength (λ) of an exposure device, a numerical aperture of the lens (NA), an illumination shape (σ, ε), a phase/a transmissivity of a mask, and the like are changed.
In order to solve those problems, a method and a system for simultaneously deciding appropriate D. R. and process parameters are proposed. By using the method and the system, not only D. R., but also process parameters with which a pattern drawn by the D. R. can be faithfully formed on a wafer can be simultaneously decided.
However, when portions A and B of the layout are focused on at the time of sequentially deciding D. R. and process parameters by using the above-described method and system, there occur some cases in which it is difficult to decide D. R. and to decide process parameters. For example, no problem is brought about under a certain D. R. 1 and a problem is brought about under the other D. R. 2 in the A portion, and in contrast thereto, a problem is brought about under D. R. 1 and no problem is brought about under the other D. R. 2 in the B portion.
Moreover, it is assumed that a partial correction in design pattern is carried out with respect to a mask once prepared, and the mask is prepared again. In this case, when parameters different from those with respect to the mask prepared already are optimum (i.e., it is necessary to change the process parameters) as a result that process parameters are optimized with respect to the design change part, there is the problem that all the layout portions other than the corrected part are made different from the mask prepared already.
In that case, it is necessary to carry out reliability evaluation under new conditions from the standpoint of the reliability of a device, which takes a great deal of time. Further, although only some portions of the design pattern have been corrected, it is necessary to carry out mask data process which takes a great deal of time onto all the patterns again. TAT is made extremely long due to such twice reliability evaluation and mask data process.